Without limiting the scope of the invention, its background is described in connection with a synchronous circuit coupled to an asynchronous bus interface.
In systems using an asynchronous bus to couple devices, the receiving device contains synchronous circuitry which must reliably detect and respond to signals and events present on the asynchronous bus. To accomplish this the asynchronous signal present at the bus interface must be synchronized to the time domain used within the receiving circuit.
Heretofore, in the design of logic coupled to asynchronous bus circuitry, the typical approach to these problems is to provide a two clock synchronizer which receives the incoming asynchronous signal into a pair of serially coupled registers clocked on the clock of the synchronous circuitry time domain, so that a metastable condition on the first register caused by a transition in the asynchronous signal or event is not transferred to the output of the second register, effectively isolating the asynchronous event from the synchronous time domain and preventing errors caused by metastability due to transitions at or near the clock edges. In order for the prior art approach to function it is required that the asynchronous event or signal being detected or observed have a pulse width greater than at least 1 of the synchronous clocks in duration; alternatively handshaking protocols can be used where the asynchronous event is required to remain present until the synchronous receiving circuit acknowledges that it has successfully captured the event. Both of these approaches undesirably restrict the asynchronous signals and result in slower throughput than is desirable on the asynchronous bus.
A need for an easily implemented method and apparatus for reliably synchronizing asynchronous signals or events without unduly restricting the duration of such signals or events on an asynchronous bus thus exists. Accordingly, improvements which overcome any or all of these problems are presently desirable.